高级模拟设计工程师（高速/PLL）

Analog Design Engineer-High Speed IO
Responsibility:
1. Design, simulation and verification of high speed CMOS analog and mixed-signal circuits.
2. Co-work with layout engineer for physical implementation.
3. Help define specifications of IC blocks and create design documentation.
4. Silicon test, characterization and debugging.

Qualification:
MSEE.
1. Solid knowledge and experience in high speed analog and mixed-signal circuit design.
2. Experience in high speed I/O related area (SerDes, Transmitter, Receiver, DDR IO interface, etc) is a plus.
3. Good understanding of deep submicron CMOS technology process and device physics.
4. Proficiency of EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc).
5. Experiences in Verilog, Verilog-A, Python, and/or Matlab

Analog Design Engineer-PLL
Responsibility:
1. Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
2. Oversee layout and verification activities which include floor plan, LVS and DRC.

Qualification:
1. Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
2. Oversee layout and verification activities which include floor plan, LVS and DRC.
Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
3. Oversee layout and verification activities which include floor plan, LVS and DRC.
4. Master degree in ASIC Design Relevant;
5. Good fundamental in analysis and design of analog / mixed-signal circuits; Experience in Verilog, AHDL and/or Matlab; Ability to do layout and provide verification/debugging guidance; Solid knowledge of EDA design tools (Analog artist, spectre, HSPICE and nc-verilog ...); Familiar with Computer languages such as C, C++, perl;
6. Experience in any of the following areas is preferred: PLL, high-speed I/O’s;
7. Good communication skills and Good oral/written English.