Responsibility: 1. Micro-architecture definition/writing IC design spec; 2. RTL coding for logic modules; 3. Simulation/Verification of functionalities at both module level and top level; 4. Do module level synthesis / timing analysis; 5. Writing complete design/verification reports; 6. Silicon debug of the related module functionalities; 7. Writing test patterns for production tests.
Qualification: 1. MSEE with minimum 4-year experience of digital design experience; 2. Relevant experience in high-speed and low power digital design is must; 3. Solid knowledge of digital design building blocks (eg. Data-path, Synchronizer, FIFO...); 4. Strong skills of Verilog RTL coding and verification and debug; 5. Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc; 6. Relevant experience in DDR interface design is a plus; 7. Self-motivated and team player.